The KSZ9567 is a fully integrated layer 2, managed, seven-port gigabit Ethernet switch with numerous advanced features. Five of the seven ports incorporate 10/100/1000 Mbps PHYs. The other two ports have interfaces that can be configured as SGMII, RGMII, MII or RMII. Either of these may connect directly to a host processor or to an external PHY. The SGMII port may interface to a fiber optic transceiver.

Full register access is available by SPI or I²C interfaces, and by optional in-band management via any of the data ports. PHY register access is provided by a MIIM interface.

Security features include support for IEEE 802.1X port-based authentication and Access Control List (ACL) filtering.

As a member of the EtherSynch^® product family, the KSZ9567 incorporates full hardware support for the IEEE 1588v2 Precision Time Protocol (PTP), including hardware time-stamping at all PHY-MAC interfaces, and a high-resolution hardware “PTP clock”. IEEE 1588 provides sub-microsecond synchronization for a range of industrial Ethernet applications.

The KSZ9567 fully supports time-stamping and time-keeping features support IEEE 802.1AS time synchronization. All ports feature credit based traffic shapers for IEEE 802.1Qav, and a time aware scheduler as proposed for IEEE 802.1Qbv.

An assortment of power-management features including Energy-Efficient Ethernet (EEE) have been designed in to satisfy energy efficient environments.

Looking for a Linux^® Host Processor, try the SAMA5D3.

Microchip's complimentary and confidential MicroCHECK design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account.

KSZ9567 国产替代 型号

KSZ9567 国产替代型号