OUTLINE DIMENSIONS

ADMV8818SCCZ-EP-R2

Tunable Filters56-Terminal Land Grid Array [LGA]

TUNABLE FILTER 2GHZ TO 18GHZ 56LGA

The ADMV8818SCCZ-EP-R2 is a 2 GHz to 18 GHz digitally tunable high-pass and low-pass filter MMIC in a 56-terminal LGA package, operating from -55°C to +105°C with SPI control.Checked against the datasheet

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Technical parameters

Datasheet-verified parameters

25 items

Parameter	Value and test conditions	Source
Package	56-Terminal Land Grid Array [LGA], 2'' Tape and Reel, CC-56-3
Operating Temperature Range	-55°C to +105°C
Grade	Enhanced Product (AQEC standard), Military
RoHS	Compliant (Z = RoHS Compliant Part)
Frequency Range	2 GHz to 18 GHz
Typical Insertion Loss	9 dB
Wideband Rejection	35 dB
Maximum Bandwidth	4 GHz
VDD1 Supply Voltage	2.5 V
VDD2 Supply Voltage	3.3 V
VSS1 Supply Voltage	-2.5 V
VDD1 Absolute Maximum Rating	-0.3 V to +2.8 V
VDD2 Absolute Maximum Rating	-0.3 V to +3.6 V
VSS1 Absolute Maximum Rating	-3.6 V to +0.3 V
Digital Control Inputs Voltage Absolute Maximum Rating	-0.3 V to VDD2 + 0.3 V
Digital Control Inputs Current Absolute Maximum Rating	2 mA
RF Input Power Absolute Maximum Rating	20 dBm
Storage Temperature Range	-65°C to +150°C
Junction Temperature for 1,000,000 Hours MTTF	135°C
Nominal Junction Temperature	90°C (T_PADDLE = 85°C)
Moisture Sensitivity Level (MSL) Rating	MSL3
RF Input Impedance	50 Ω (dc-coupled)
RF Output Impedance	50 Ω (dc-coupled)
SPI Logic Level	3.3 V
Filter State Bits	4 bits (16 states)

All parameters (8)ExpandCollapse

Power
SUPPLY VOLTAGE VDD1	2.5 V (Typ)
SUPPLY VOLTAGE VDD2	3.3 V (Typ)
SUPPLY VOLTAGE VSS1	-2.5 V (Typ)
AC and DC characteristics
FREQUENCY RANGE (f3dB)	2 GHz to 18 GHz
Environment and package
Package	56-Terminal Land Grid Array [LGA]
Other
INSERTION LOSS	9 dB (Typ)
Operating Range	-55°C to +105°C
WIDEBAND REJECTION	35 dB

Pinout and package

Package56-Terminal Land Grid Array [LGA], 2'' Tape and Reel, CC-56-3

Pin	Name	Function	Source
7		RFIN: RF Input Pin. dc-coupled and matched to 50 Ω. Do not apply an external voltage.
14		RST: Chip Reset. 3.3 V logic. Active low. Internally pulled high with a 260 kΩ resistor.
16		SCLK: SPI Clock. 3.3 V logic. Internally pulled low with a 260 kΩ resistor.
18		CS: SPI Chip Select. 3.3 V logic. Active low. Internally pulled low with a 260 kΩ resistor.
20		SDO: SPI Data Output. 3.3 V logic. Internally pulled low with a 260 kΩ resistor.
22		SDI: SPI Data Input. 3.3 V logic. Internally pulled low with a 260 kΩ resistor.
24		SFL: SPI Fast Latch Enable. 3.3 V logic. Set high to enable fast latching of filter states on each rising edge of CS. Internally pulled low with a 260 kΩ resistor.
31		VDD1: 2.5 V Power Supply Pin. Place 0.1 μF and 100 pF decoupling capacitors close to VDD1.
36		RFOUT: RF Output Pin. dc-coupled and matched to 50 Ω. Do not apply an external voltage.
39		VDD2: 3.3 V Power Supply Pin. Place 0.1 μF and 100 pF decoupling capacitors close to VDD2.
41		VSS1: -2.5 V Power Supply Pin. Place 0.1 μF and 100 pF decoupling capacitors close to VSS1.
1-6, 8-13, 15, 17, 1		GND: Ground. Connect to RF and dc ground.
EPAD		EPAD: Exposed Pad. Must be connected to the RF and dc ground.

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DatasheetDatasheet · 1.2 MB · 2026-10-27

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