AT17LV512-10CU
Microchip TechnologyUnited States

AT17LV512-10CU

ActiveConfiguration Proms for FPGAs8CN4

IC SRL CONFIG EEPROM 512K 8-LAP

AT17LV512-10CU is a 512-Kbit FPGA configuration EEPROM supporting 3.0V to 5.5V supply, in an 8-lead LAP package, with industrial temperature range -40°C to +85°C and RoHS compliant lead-free/halogen-free features.Checked against the datasheet

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Technical parameters

Datasheet-verified parameters

22 items
ParameterValue and test conditionsSource
Package8CN4, 8-lead LAP
Operating Temperature-40°C to +85°C
GradeIndustrial
RoHSCompliant (Lead-free/Halogen-free)
Halogen FreeYes
Memory Size512-Kbit (524,288 x 1-bit)
Recommended Operating Voltage3.0V to 5.5V
Absolute Maximum Rating: Operating Temperature-40°C to +85°C
Absolute Maximum Rating: Storage Temperature-65°C to +150°C
Absolute Maximum Rating: Supply Voltage-0.5V to +7.0V
Absolute Maximum Rating: Voltage on Any Pin-0.1V to VCC +0.5V
Absolute Maximum Rating: ESD2000V (RZAP = 1.5K, CZAP = 100pF)
High-level Input VoltageMin: 2.0V, Max: VCC (VCC = 3.3V ± 10%)
Low-level Input VoltageMin: 0V, Max: 0.8V (VCC = 3.3V ± 10%)
High-level Output VoltageMin: 2.4V (IOH = -2mA, VCC = 3.3V ± 10%)
Low-level Output VoltageMax: 0.4V (IOL = +3mA, VCC = 3.3V ± 10%)
Supply Current, Active ModeMax: 5mA (VCC = 3.3V ± 10%)
Supply Current, Standby ModeMax: 100μA (VCC = 3.3V ± 10%)
Input or Output Leakage CurrentMin: -10μA, Max: 10μA (VIN = VCC or GND, VCC = 3.3V ± 10%)
Endurance100,000 Write Cycles
Data Retention90 Years (at 85°C)
Lead FinishCuNiAu (Lead-free/Halogen-free)
All parameters (12)ExpandCollapse
Power
Voltage - Supply3V ~ 3.6V, 4.5V ~ 5.5V
Environment and package
Memory Size512kb
Mounting TypeSurface Mount
Operating Temperature-40°C~85°C
PackageTube
Package / Case8-TDFN
Supplier Device Package8-LAP (6x6)
Other
Base Product NumberAT17LV512
MfrMicrochip Technology
Product StatusActive
Programmable TypeSerial EEPROM
Series-

Pinout and package

Figure 1-1. Pinouts (1)
Figure 1-1. Pinouts (1)
Package: 8CN4, 8-lead LAP
PinNameFunctionSource
1DATA: Three-state Data Output for Configuration. Open-collector bi-directional pin for programming.
2CLK: Clock Input. Used to increment the internal address and bit counter for reading and programming.
3RESET/OE: RESET (Active Low) / Output Enable (Active High) when SER_EN is High. Logic polarity is programmable.
4CE: Chip Enable Input (Active Low). A Low level allows CLK to increment the address counter and enables the data output driver.
5GND: Ground. A 0.2μF decoupling capacitor between VCC and GND is recommended.
6CEO: Chip Enable Output (Active Low). Goes Low when the address counter has reached its maximum value. Used for daisy chaining.
7SER_EN: Serial Enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the 2-wire Serial Programming Mode.
8VCC: Power Supply. 3.3V (±10%) and 5.0V (±10%) power supply pin.

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DatasheetDatasheet · 669.5 KB · 2026-11-03
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