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Technical parameters

Key specs

Max frequency230 MHzMax
Outputs5
Supply voltage1.7 ~ 1.9 V

Datasheet-verified parameters

22 items
ParameterValue and test conditionsSource
Maximum output frequency230 MHz
Number of outputs5
Supply voltageVDD: 1.7 V (Min) to 1.9 V (Max); VDDOUT: 2.3 V (Min) to 3.6 V (Max) for CDCE925
PackageTSSOP (PW), 16 Pins
Operating temperature-40 °C to 85 °C
RoHSYes
Recommended Operating ConditionsVDD: 1.7 V (Min) to 1.9 V (Max); VDDOUT: 2.3 V (Min) to 3.6 V (Max); TA: -40 °C to 85 °C
Absolute Maximum RatingsVDD: -0.5 V to 2.5 V; TJ: 125 °C; Tstg: -65 °C to 150 °C
Supply currentTyp 20 mA (All PLLs on, fCLK=27MHz, fVCO=135MHz, fOUT=27MHz, All outputs off)
Output supply currentTyp 2 mA (CDCE925, VDDOUT=3.3V, No load, all outputs on, fOUT=27MHz)
Power-down currentTyp 30 μA (fIN=0MHz, VDD=1.9V)
VCO frequency range80 MHz (Min) to 230 MHz (Max)
LVCMOS high-level output voltageMin 2.9 V (VDDOUT=3V, IOH=-0.1mA); Min 2.4 V (VDDOUT=3V, IOH=-8mA); Min 2.2 V (VDDOUT=3V, IOH=-12mA)
LVCMOS low-level output voltageMax 0.1 V (VDDOUT=3V, IOL=0.1mA); Max 0.5 V (VDDOUT=3V, IOL=8mA); Max 0.8 V (VDDOUT=3V, IOL=12mA)
Propagation delayTyp 3.2 ns (All PLL bypass)
Rise and fall timeTyp 0.6 ns (VDDOUT=3.3V, 20%-80%)
Crystal input frequency8 MHz (Min) to 32 MHz (Max), Nom 27 MHz
ESD protectionHBM: ±2000 V; CDM: ±1500 V
Thermal resistanceRθJA: 101 °C/W (Airflow 0 LFM); RθJC(top): 42 °C/W
Input capacitanceTyp 6 pF (at Xin/Clk); Typ 2 pF (at Xout); Typ 3 pF (at S0/S1/S2)
Output loadMax 15 pF (LVCMOS)
Output currentMax ±12 mA (VDDOUT=3.3V); Max ±10 mA (VDDOUT=2.5V)
All parameters (19)ExpandCollapse
Power
Voltage - Supply1.7V ~ 1.9V
AC and DC characteristics
Frequency - Max230MHz
Environment and package
Mounting TypeSurface Mount
Operating Temperature-40°C~85°C
PackageTape & Reel (TR); Cut Tape (CT); Digi-Reel®
Package / Case16-TSSOP (0.173", 4.40mm Width)
Supplier Device Package16-TSSOP
Other
Base Product NumberCDCE925
Differential - Input:OutputNo/No
Divider/MultiplierYes/No
InputLVCMOS, Crystal
MfrTexas Instruments
Number of Circuits1
OutputLVCMOS
PLLYes with Bypass
Product StatusActive
Ratio - Input:Output1:5
Series-
TypePLL Clock Generator

Pinout and package

Figure 4-1. PW Package 16-Pin …
Figure 4-1. PW Package 16-Pin …
Package: TSSOP (PW), 16 Pins
PinNameFunctionSource
1Xin/CLK: Crystal oscillator input or LVCMOS clock input
2S0: User-programmable control input
3VDD: 1.8-V power supply for the device
4VCtrl: VCXO control voltage
5GND: Ground
6VDDOUT: CDCE925 output supply (2.5V or 3.3V)
7Y4: LVCMOS output
8Y5: LVCMOS output
9VDDOUT: CDCE925 output supply (2.5V or 3.3V)
10Y3: LVCMOS output
11Y2: LVCMOS output
12GND: Ground
13Y1: LVCMOS output
14SCL/S2: Serial clock input or user-programmable control input
15SDA/S1: Bidirectional serial data input/output or user-programmable control input
16Xout: Crystal oscillator output

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