Figure 4. 48-Lead LQFP (ST-48)…
Analog Devices Inc.United States
IC ADC 16BIT SAR 48LQFP
The AD7655ASTZ is a 16-bit, 4-channel, 1 MSPS PulSAR SAR analog-to-digital converter in a 48-lead LQFP package, featuring single 5 V supply operation and serial/parallel interfaces, with an operating temperature range of -40°C to +85°C.Checked against the datasheet
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View full reportTechnical parameters
Key specs
Resolution16 bit
Sampling rate1 MSPSMax
Inputs4
InterfaceQSPI / OSPI
Supply voltage≥ 5 V
Datasheet-verified parameters
15 items| Parameter | Value and test conditions | Source |
|---|---|---|
| Resolution | 16-bit | |
| Throughput | 1 MSPS (normal mode), 888 kSPS (impulse mode) | |
| Channels | 4-channel | |
| Interface | Parallel and serial 5 V/3 V interface, SPI/QSPI/MICROWIRE/DSP compatible | |
| Supply Voltage | Single 5 V supply operation | |
| Package | 48-lead Low Profile Quad Flat Package (LQFP) ST-48 |
All parameters (22)
| Power | |
|---|---|
| Voltage - Supply, Analog | 5V |
| Voltage - Supply, Digital | 5V |
| Environment and package | |
| Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 85°C |
| Package | Tray |
| Package / Case | 48-LQFP |
| Supplier Device Package | 48-LQFP (7x7) |
| Other | |
| Architecture | SAR |
| Base Product Number | AD7655 |
| Configuration | MUX-S/H-MUX-ADC |
| Data Interface | SPI, Parallel, DSP |
| Features | Simultaneous Sampling |
| Input Type | Pseudo-Differential, Single Ended |
| Mfr | Analog Devices Inc. |
| Number of A/D Converters | 1 |
| Number of Bits | 16 |
| Number of Inputs | 2, 4 |
| Product Status | Active |
| Ratio - S/H:ADC | 2:1 |
| Reference Type | External |
| Sampling Rate (Per Second) | 1M |
| Series | PulSAR® |
Pinout and package
Figure 4. 48-Lead LQFP (ST-48)…
| Pin | Name | Function | Source |
|---|---|---|---|
| 2 | AVDD, Input Analog Power Pin. Nominally 5 V | ||
| 3 | A0, Multiplexer Select. When LOW, INA1 and INB1 are sampled; When HIGH, INA2 and INB2 are sampled | ||
| 4 | BYTESWAP, Parallel Mode Selection (8 Bit, 16 Bit). When LOW, LSB on D[7:0]; When HIGH, LSB on D[15:8] | ||
| 5 | A/B, Data Channel Selection. In parallel mode, LOW reads Channel B, HIGH reads Channel A. In serial mode, HIGH outputs Channel A first | ||
| 7 | IMPULSE, Mode Selection. When HIGH, selects reduced power mode | ||
| 8 | SER/PAR, Serial/Parallel Selection Input. When LOW, parallel port selected; When HIGH, serial interface mode selected | ||
| 13 | D[4] or EXT/INT, Bit 4 in parallel mode; Internal/External clock select in serial mode, LOW for internal, HIGH for external | ||
| 14 | D[5] or INVSYNC, Bit 5 in parallel mode; SYNC active state select in serial mode, LOW for active HIGH, HIGH for active LOW | ||
| 15 | D[6] or INVSCLK, Bit 6 in parallel mode; SCLK inversion control in serial mode | ||
| 16 | D[7] or RDC/SDIN, Bit 7 in parallel mode; External data input or read mode selection in serial mode | ||
| 17 | OGND, Input/Output Interface Digital Power Ground | ||
| 18 | OVDD, Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V) | ||
| 21 | D[8] or SDOUT, Bit 8 in parallel mode; Serial data output in serial mode | ||
| 22 | D[9] or SCLK, Bit 9 in parallel mode; Serial data clock input or output in serial mode | ||
| 23 | D[10] or SYNC, Bit 10 in parallel mode; Frame synchronization output in serial mode | ||
| 24 | D[11] or RDERROR, Bit 11 in parallel mode; Incomplete read error flag in serial slave mode | ||
| 29 | BUSY, Busy Output. Transitions HIGH when conversion starts, remains HIGH until conversions complete and data latched | ||
| 30 | EOC, End of Convert Output. Goes LOW at each channel conversion | ||
| 31 | RD, Read Data. When CS and RD are both LOW, interface output bus is enabled | ||
| 32 | CS, Chip Select. When CS and RD are both LOW, interface output bus is enabled. Also gates external serial clock | ||
| 33 | RESET, Reset Input. When HIGH, resets AD7655, aborts current conversion | ||
| 34 | PD, Power-Down Input. When HIGH, power consumption reduced and conversions inhibited | ||
| 35 | CNVST, Convert Start | ||
| 37 | REF, Reference Voltage Input | ||
| 38 | REFGND, Reference Ground | ||
| 39 | INB1, Analog Input B1 | ||
| 40 | INBN, Analog Input B Negative | ||
| 41 | INB2, Analog Input B2 | ||
| 42 | REFB, Reference Voltage B | ||
| 43 | REFA, Reference Voltage A | ||
| 44 | INA2, Analog Input A2 | ||
| 45 | INAN, Analog Input A Negative | ||
| 46 | INA1, Analog Input A1 | ||
| 1, 47, 48 | AGND, Analog Power Ground Pin | ||
| 11, 12 | D[2:3] or DIVSCLK[0:1], Bit 2 and Bit 3 in parallel mode; Serial clock divider inputs in serial master read mode | ||
| 19, 36 | DVDD, Digital Power. Nominally at 5 V | ||
| 25 to 28 | D[12:15], Bit 12 to Bit 15 of the parallel port data output bus | ||
| 6, 20 | DGND, Digital Power Ground | ||
| 9, 10 | D[0:1], Bit 0 and Bit 1 of the Parallel Port Data Output Bus |
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