Figure 7. Pin Configuration
Analog Devices Inc.United States
IC ADC 24BIT SIGMA-DELTA 64LFCSP
8-channel 24-bit simultaneous sampling ADC, up to 16 kSPS, with internal PGA and 2.5V reference, 64-LFCSP package, operating temperature -40°C to +125°C, SPI interface.Checked against the datasheet
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View full reportTechnical parameters
Key specs
Resolution24 bit
Sampling rate16 kSPSMax
Inputs8
InterfaceSPI
Supply voltage1.8 ~ 3.6 V
Datasheet-verified parameters
20 items| Parameter | Value and test conditions | Source |
|---|---|---|
| Resolution | 24-bit | |
| Output Data Rate (ODR) | Up to 16 kSPS per channel | |
| Channels | 8-channel | |
| Interface | SPI, Data Output Interface | |
| Power Supply | Bipolar (±1.65 V) or unipolar (3.3 V) supplies; Digital I/O supply: 1.8 V to 3.6 V | |
| Package | 64-Lead LFCSP (9mm x 9mm w/ EP) |
All parameters (22)
| Power | |
|---|---|
| Voltage - Supply, Analog | ±1.65V, 2.2V ~ 3.6V |
| Voltage - Supply, Digital | - |
| Environment and package | |
| Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 125°C |
| Package | Tray |
| Package / Case | 64-WFQFN Exposed Pad, CSP |
| Supplier Device Package | 64-LFCSP (9x9) |
| Other | |
| Architecture | Sigma-Delta |
| Base Product Number | AD7779 |
| Configuration | PGA-ADC |
| Data Interface | Serial |
| Features | Simultaneous Sampling |
| Input Type | Differential, Single Ended |
| Mfr | Analog Devices Inc. |
| Number of A/D Converters | 8 |
| Number of Bits | 24 |
| Number of Inputs | 8 |
| Product Status | Active |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | External, Internal |
| Sampling Rate (Per Second) | 16k |
| Series | - |
Pinout and package
Figure 7. Pin Configuration
| Pin | Name | Function | Source |
|---|---|---|---|
| 1 | AIN0-, Analog Input Channel 0, Negative | ||
| 2 | AIN0+, Analog Input Channel 0, Positive | ||
| 3 | AIN1-, Analog Input Channel 1, Negative | ||
| 4 | AIN1+, Analog Input Channel 1, Positive | ||
| 5 | AVSS1A, Negative Front-End Analog Supply for Channel 0 to Channel 3, Typical at -1.65 V (Dual Supply) and AGND (Single Supply) | ||
| 6 | AVDD1A, Positive Front-End Analog Supply for Channel 0 to Channel 3, Typical at AVSSx + 3.3 V | ||
| 7 | REF1-, Negative Reference Input 1 for Channel 0 to Channel 3, Typical at AVSSx | ||
| 8 | REF1+, Positive Reference Input 1 for Channel 0 to Channel 3, Typical at REF1- + 2.5 V | ||
| 9 | AIN2-, Analog Input Channel 2, Negative | ||
| 10 | AIN2+, Analog Input Channel 2, Positive | ||
| 11 | AIN3-, Analog Input Channel 3, Negative | ||
| 12 | AIN3+, Analog Input Channel 3, Positive | ||
| 13 | MODE0/GPIO0, Mode 0 Input Pin in Pin Control Mode; Configurable General-Purpose Input/Output 0 in SPI Control Mode | ||
| 14 | MODE1/GPIO1, Mode 1 Input Pin in Pin Control Mode; Configurable General-Purpose Input/Output 1 in SPI Control Mode | ||
| 15 | MODE2/GPIO2, Mode 2 Input Pin in Pin Control Mode; Configurable General-Purpose Input/Output 2 in SPI Control Mode | ||
| 16 | MODE3/ALERT, Mode 3 Input Pin in Pin Control Mode; Alert Output Pin in SPI Control Mode | ||
| 17 | CONVST_SAR, Σ-Δ Output Interface Selection Pin in Pin Control Mode; Start for SAR conversion in SPI control mode | ||
| 18 | ALERT/CS, Alert Output Pin in Pin Control Mode; Chip Select Pin in SPI Control Mode | ||
| 19 | DCLK2/SCLK, DCLK Frequency Selection Pin 2 in Pin Control Mode; SPI Clock in SPI Control Mode | ||
| 20 | DCLK1/SDI, DCLK Frequency Selection Pin 1 in Pin Control Mode; SPI Data In in SPI Control Mode | ||
| 21 | DCLK0/SDO, DCLK Frequency Selection Pin 0 in Pin Control Mode; SPI Data Out in SPI Control Mode | ||
| 22 | DGND, Digital Ground | ||
| 23 | DREGCAP, Digital LDO Output, Decouple to DGND with 1 μF capacitor | ||
| 24 | IOVDD, Digital I/O Supply, 1.8 V to 3.6 V | ||
| 25 | DOUT3, Data Output 3 | ||
| 26 | DOUT2, Data Output 2 | ||
| 27 | DOUT1, Data Output 1 | ||
| 28 | DOUT0, Data Output 0 | ||
| 29 | DCLK, Data Clock | ||
| 30 | DRDY, Data Ready | ||
| 31 | XTAL1, Crystal 1 | ||
| 32 | XTAL2/MCLK, Crystal 2 / Master Clock | ||
| 33 | START, Start | ||
| 34 | SYNC_OUT, Synchronization Output | ||
| 35 | SYNC_IN, Synchronization Input | ||
| 36 | RESET, Reset | ||
| 37 | AIN7+, Analog Input Channel 7, Positive | ||
| 38 | AIN7-, Analog Input Channel 7, Negative | ||
| 39 | AIN6+, Analog Input Channel 6, Positive | ||
| 40 | AIN6-, Analog Input Channel 6, Negative | ||
| 41 | REF2+, Positive Reference Input 2 for Channel 4 to Channel 7, Typical at REF2- + 2.5 V | ||
| 42 | REF2-, Negative Reference Input 2 for Channel 4 to Channel 7, Typical at AVSSx | ||
| 43 | AVDD1B, Positive Front-End Analog Supply for Channel 4 to Channel 7, Typical at AVSSx + 3.3 V | ||
| 44 | AVSS1B, Negative Front-End Analog Supply for Channel 4 to Channel 7, Typical at -1.65 V (Dual Supply) and AGND (Single Supply) | ||
| 45 | AIN5+, Analog Input Channel 5, Positive | ||
| 46 | AIN5-, Analog Input Channel 5, Negative | ||
| 47 | AIN4+, Analog Input Channel 4, Positive | ||
| 48 | AIN4-, Analog Input Channel 4, Negative | ||
| 49 | REF_OUT, Internal Reference Output, 2.5 V | ||
| 50 | AVSS2B, Negative Analog Supply | ||
| 51 | AREG2CAP, Analog LDO Output 2, Decouple to AVSS with 1 μF capacitor | ||
| 52 | AVDD2B, Positive Analog Supply, 2.2 V to 3.6 V | ||
| 53 | AVSS3, Negative Analog Ground | ||
| 54 | FORMAT1, Output Data Frame 1 Selection | ||
| 55 | FORMAT0, Output Data Frame 0 Selection | ||
| 56 | CLK_SEL, Clock Source Selection | ||
| 57 | VCM, Common-Mode Voltage Output, Typical at (AVDD1 + AVSSx)/2 | ||
| 58 | AVDD2A, Analog Supply, 2.2 V to 3.6 V | ||
| 59 | AREG1CAP, Analog LDO Output 1, Decouple to AVSS with 1 μF capacitor | ||
| 60 | AVSS2A, Negative Analog Supply | ||
| 61 | AVSS4, Negative SAR Analog Supply and Reference | ||
| 62 | AVDD4, Positive SAR Analog Supply and Reference Source | ||
| 63 | AUXAIN+, Positive SAR Analog Input Channel | ||
| 64 | AUXAIN-, Negative SAR Analog Input Channel |
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