Analog Devices Inc.United States
IC ENERGY METER MULTIFUN 40LFCSP
ADE7858AACPZ is a high-accuracy 3-phase energy metering IC supporting active, reactive, and apparent energy measurement, in a 40-lead LFCSP package, operating from -40°C to +85°C, and RoHS compliant.Checked against the datasheet
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Datasheet-verified parameters
23 items| Parameter | Value and test conditions | Source |
|---|---|---|
| Package | 40-Lead Lead Frame Chip Scale Package [LFCSP] | |
| Operating Temperature | -40°C to +85°C | |
| Grade | Industrial Range | |
| RoHS | RoHS Compliant | |
| Storage Temperature Range | -65°C to +150°C | |
| VDD Pin (PSM0 Mode) | Min: 2.97 V, Max: 3.63 V |
All parameters (16)
| Power | |
|---|---|
| Current - Supply | 20mA |
| Voltage - I/O High | 2V, 2.4V |
| Voltage - I/O Low | 0.4V, 0.8V |
| Voltage - Supply | 2.8 V ~ 3.7 V |
| AC and DC characteristics | |
| Input Impedance | 400kOhm |
| Environment and package | |
| Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 85°C |
| Package | Tray |
| Package / Case | 40-WFQFN Exposed Pad, CSP |
| Supplier Device Package | 40-LFCSP-WQ (6x6) |
| Other | |
| Base Product Number | ADE7858 |
| Measurement Error | 0.2% |
| Meter Type | 3 Phase |
| Mfr | Analog Devices Inc. |
| Product Status | Active |
| Series | - |
Pinout and package
Figure 9. Pin Configuration
| Pin | Name | Function | Source |
|---|---|---|---|
| 2 | PM0: Power Mode Pin 0. The PM0 and PM1 pins together specify the power mode of the ADE7858A. | ||
| 3 | PM1: Power Mode Pin 1. The PM1 and PM0 pins together specify the power mode of the ADE7858A. | ||
| 4 | RESET: Reset Input, Active Low. In PSM0 mode, this pin must stay low for at least 10 μs to trigger a hardware reset. | ||
| 5 | DVDD: 2.5 V Output of the Digital Low Dropout (LDO) Regulator. Decouple this pin with a 4.7 μF capacitor in parallel with a ceramic 220 nF capacitor. Do not connect external active circuitry to this pin. | ||
| 6 | DGND: Ground Reference for the Digital Circuitry. | ||
| 17 | REF_IN/OUT: The REF_IN/OUT pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.2 V. An external reference source with 1.2 V ± 8% can also be connected at this pin. In either case, decouple REF_IN/OUT to AGND with a 4.7 μF capacitor in parallel with a | ||
| 20 | REF_GND: Ground Reference, Internal Voltage Reference. Connect REF_GND to the analog ground plane. | ||
| 24 | AVDD: 2.5 V Output of the Analog Low Dropout (LDO) Regulator. Decouple this pin with a 4.7 μF capacitor in parallel with a ceramic 220 nF capacitor. Do not connect external active circuitry to this pin. | ||
| 25 | AGND: Ground Reference for the Analog Circuitry. Tie AGND to the analog ground plane or to the quietest ground reference in the system. Use this quiet ground reference for all analog circuitry, for example, antialiasing filters, current transducers, and voltage transducers. | ||
| 26 | VDD: Supply Voltage. The VDD pin provides the supply voltage. In PSM0 (normal power) mode, maintain the supply voltage at 3.3 V ± 10% for specified operation. In PSM1 (reduced power) mode, PSM2 (low power) mode, and PSM3 (sleep) mode, when the ADE7868A or ADE7878A is supplied from a battery, maintai | ||
| 27 | CLKIN: Master Clock. An external clock can be provided at this logic input. Alternatively, a crystal can be connected across the CLKIN and CLKOUT pins to provide a clock source for the ADE7858A. The clock frequency for specified operation is 16.384 MHz. For information about choosing a suitable | ||
| 28 | CLKOUT: Crystal Output. A crystal can be connected across the CLKIN and CLKOUT pins to provide a clock source for the ADE7858A. The clock frequency for specified operation is 16.384 MHz. For information about choosing a suitable crystal, see the Crystal Circuit section. | ||
| 36 | SCLK/SCL: Serial Clock Input for the SPI Port/Serial Clock Input for the I2C Port. All serial data transfers synchronize to this clock (see the Serial Interfaces section). The SCLK/SCL pin has a Schmitt trigger input for use with a clock source that has a slow edge transition time, for example, opto | ||
| 37 | MISO/HSD: Data Output for the SPI Port/Data Output for the HSDC Port. | ||
| 38 | MOSI/SDA: Data Input for the SPI Port/Data Input and Output for the I2C Port. | ||
| 39 | SS/HSA: Slave Select for the SPI Port/HSDC Port Active. | ||
| 1, 10, 11, 21, 30, 3 | NC: No Connect. These pins are not connected internally. It is recommended that these pins be grounded. | ||
| 13, 14 | ICP, ICN: Analog Inputs, Current Channel C. Current Channel C is used with the current transducers. The ICP (positive) and ICN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±0.5 V peak. Channel C also has an internal PGA, which is set to the same value, | ||
| 15, 16 | INP, INN: Analog Inputs, Neutral Current Channel N. Current Channel N is used with the current transducers. The INP (positive) and INN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±0.5 V peak. Channel N also has an internal PGA, which is separate from | ||
| 18, 19, 22, 23 | VN, VCP, VBP, VAP: Analog Inputs, Voltage Channels. These channels are used with the voltage transducer. The VN, VCP, VBP, and VAP inputs are single-ended voltage inputs with a maximum signal level of ±0.5 V peak with respect to VN for specified operation. Each voltage channel also has an internal | ||
| 29, 32 | IRQ0, IRQ1: Interrupt Request Outputs. These pins are active low logic outputs. For information about events that trigger interrupts, see the Interrupts section. | ||
| 33, 34, 35 | CF1, CF2, CF3/HSCLK: Calibration Frequency Logic Outputs/Serial Clock Output of the HSDC Port. The CF1, CF2, and CF3/HSCLK outputs provide power information based on the CF1SEL[2:0], CF2SEL[2:0], and CF3SEL[2:0] bits in the CFMODE register. Use these outputs for operational and calibration purposes. | ||
| 7, 8 | IAP, IAN: Analog Inputs, Current Channel A. Current Channel A is used with the current transducers. The IAP (positive) and IAN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±0.5 V peak. Channel A also has an internal PGA, which is set to the same value, | ||
| 9, 12 | IBP, IBN: Analog Inputs, Current Channel B. Current Channel B is used with the current transducers. The IBP (positive) and IBN (negative) inputs are fully differential voltage inputs with a maximum differential level of ±0.5 V peak. Channel B also has an internal PGA, which is set to the same value, | ||
| EP | EP: Exposed Pad. Create a similar pad on the printed circuit board (PCB) under the exposed pad. Solder the exposed pad to the pad on the PCB to confer mechanical strength to the package. Connect the pads to AGND and DGND. |
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