Figure 3. Pin Configuration

Figure 3. Pin Configuration

Analog Devices Inc.United States

ADE9000ACPZ-RL

ActiveAnalog Front End (AFE)40-Lead Lead Frame Chip Scale Package [LFCSP]

IC AFE 7 CHAN 40LFCSP-WQ

ADE9000ACPZ-RL is a high-precision multiphase energy and power quality monitoring IC, integrating 7 high-performance ADCs and a DSP engine, supporting IEC 61000-4-30 standard, in a 40-LFCSP package, with an operating temperature range of -40°C to +85°C.Checked against the datasheet

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Technical parameters

Datasheet-verified parameters

23 items
ParameterValue and test conditionsSource
Package40-Lead Lead Frame Chip Scale Package [LFCSP], 13'' Tape and Reel, CP-40-7
Operating Temperature-40°C to +85°C
GradeIndustrial Range
RoHSRoHS Compliant Part (Z = RoHS Compliant Part)
Supply Voltage (VDD)Min: 2.97 V, Typ: 3.3 V, Max: 3.63 V
Absolute Maximum Ratings: VDD-0.3 V to +3.96 V
Absolute Maximum Ratings: Analog Input Voltage-2 V to +2 V
Absolute Maximum Ratings: Junction Temperature125°C
Absolute Maximum Ratings: Storage Temperature Range-65°C to +150°C
Supply Current (PSM0)Typ: 15 mA, Max: 17 mA (Normal mode)
Supply Current (PSM3)Typ: 90 nA, Max: 300 nA (Idle, VDD = 3.3 V, AVDD = 0 V, DVDD = 0 V)
Number of ADCs7 high performance ADCs
Signal-to-Noise Ratio (SNR)101 dB
Input Voltage Range±1 V, 707 mV rms FS at gain = 1
Channel Drift±25 ppm/°C maximum
Temperature Sensor Accuracy±3°C accuracy from −40°C to +85°C
SPI Interface Speed20 MHz
ESD Protection (HBM)4 kV
ESD Protection (MM)300 V
ESD Protection (FICDM)1.25 kV
Internal Reference Voltage1.25 V nominal
Analog LDO Output1.9 V
Digital LDO Output1.7 V
All parameters (12)ExpandCollapse
Power
Number of Channels7
Voltage - Supply, Analog3.3V
Voltage - Supply, Digital3.3V
Environment and package
Mounting TypeSurface Mount
PackageTape & Reel (TR) Cut Tape (CT) Digi-Reel®
Package / Case40-WFQFN Exposed Pad, CSP
Supplier Device Package40-LFCSP-WQ (6x6)
Other
Base Product NumberADE9000
MfrAnalog Devices Inc.
Number of Bits-
Product StatusActive
Series-

Pinout and package

Figure 3. Pin Configuration
Figure 3. Pin Configuration
Package: 40-Lead Lead Frame Chip Scale Package [LFCSP], 13'' Tape and Reel, CP-40-7
PinNameFunctionSource
1PULL_HIGH: Pull High. Tie this pin to VDD.
2DGND: Digital Ground. This pin provides the ground reference for the digital circuitry in the ADE9000.
3DVDDOUT: 1.8 V Output of the Digital Low Dropout Regulator (LDO).
4PM0: Power Mode Pin 0. PM0, combined with PM1, defines the power mode.
5PM1: Power Mode Pin 1. PM1 combined with PM0, defines the power mode.
6RESET: Reset Input, Active Low.
7IAP: Analog Inputs, Channel IA (positive). Fully differential voltage inputs with a maximum differential level of ±1 V.
8IAN: Analog Inputs, Channel IA (negative). Fully differential voltage inputs with a maximum differential level of ±1 V.
9IBP: Analog Inputs, Channel IB (positive). Fully differential voltage inputs with a maximum differential level of ±1 V.
10IBN: Analog Inputs, Channel IB (negative). Fully differential voltage inputs with a maximum differential level of ±1 V.
11ICP: Analog Inputs, Channel IC (positive). Fully differential voltage inputs with a maximum differential level of ±1 V.
12ICN: Analog Inputs, Channel IC (negative). Fully differential voltage inputs with a maximum differential level of ±1 V.
13INP: Analog Inputs, Channel IN (positive). Fully differential voltage inputs with a maximum differential level of ±1 V.
14INN: Analog Inputs, Channel IN (negative). Fully differential voltage inputs with a maximum differential level of ±1 V.
15REFGND: Ground Reference, Internal Voltage Reference.
16REF: Voltage Reference. The REF pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.25 V.
17NC1: No Connection. It is recommended to tie this pin to ground.
18NC2: No Connection. It is recommended to tie this pin to ground.
19VAN: Analog Inputs, Channel VA (negative). Fully differential voltage inputs with a maximum differential level of ±1 V.
20VAP: Analog Inputs, Channel VA (positive). Fully differential voltage inputs with a maximum differential level of ±1 V.
21VBN: Analog Inputs, Channel VB (negative). Fully differential voltage inputs with a maximum differential level of ±1 V.
22VBP: Analog Inputs, Channel VB (positive). Fully differential voltage inputs with a maximum differential level of ±1 V.
23VCN: Analog Inputs, Channel VC (negative). Fully differential voltage inputs with a maximum differential level of ±1 V.
24VCP: Analog Inputs, Channel VC (positive). Fully differential voltage inputs with a maximum differential level of ±1 V.
25AVDDOUT: 1.9 V Output of the Analog Low Dropout Regulator (LDO).
26AGND: Analog Ground Reference.
27VDD: Supply Voltage.
28GND: Supply Ground Reference.
29CLKIN: Crystal/Clock Input.
30CLKOUT: Crystal Output.
31IRQ0: Interrupt Request Output. This pin is an active low logic output.
32IRQ1: Interrupt Request Output. This pin is an active low logic output.
33CF1: Calibration Frequency (CF) Logic Output 1.
34CF2: CF Logic Output 2.
35CF3/ZX: CF Logic Output 3/Zero Crossing.
36CF4/EVENT/DREADY: CF Logic Output 4/Event Pin/Data Ready.
37SCLK: Serial Clock Input for the SPI Port.
38MISO: Data Output for the SPI Port.
39MOSI: Data Input for the SPI Port.
40SS: Slave Select for the SPI Port.
EPADEPAD: Exposed Pad. Create a similar pad on the printed circuit board (PCB) under the exposed pad. Solder the exposed pad to the pad on the PCB to confer mechanical strength to the package and connect all grounds (GND, AGND, DGND, and REFGND) together at this point.

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