Overview
A power supply's ability to recover from a sudden change in input voltage or load current depends on its control loop, power stage, and the parasitic elements in the test path. Line- and load-transient tests inject broadband excitation into the system and reveal overshoot, undershoot, recovery time, and sustained oscillation. This article relates those time-domain observations to loop behavior, then explains how to build practical step generators and interpret measured waveforms.
A line-transient test is not the same as a power-supply rejection ratio measurement. PSRR is generally treated as a dc or small-signal parameter, whereas a voltage step contains Fourier components over a broad frequency range. A load-transient test follows the same principle but injects a current step at the output; a line-transient test applies the disturbance at the input.
What Step Tests Reveal About the Control Loop
If the edge rate of an ideal line or load step approaches infinity, the step function f(t) can be represented by the following Fourier series. Real test edges are finite, but they still characterize the loop when their useful spectral content extends beyond the loop bandwidth.
How Feedback Attenuates Line and Load Disturbances
Figure 1 shows a simplified power-supply model before feedback is closed. The control-filter gain, output impedance, and input and output signals determine the output response. The input-voltage and load-current steps are represented by VIN(s) and ILOAD(s), respectively.
Figure 1 Simplified power supply model without feedback
The small-signal input-to-output filter gain is denoted by GVIN(s). For an open-loop buck converter, this gain can be written as:
ZOUT(s) is the power-stage output impedance. For a buck converter, it is:
Without feedback attenuation, disturbances in input voltage or load current transfer directly to the output. Consider a buck converter operating from VIN = 12 V at 50% duty cycle, producing 6 V. A 2 V input step ideally produces a 1 V output step. Figure 2 closes the loop around a reference, VREF, that is independent of input voltage and load current.
Figure 2 Simplified power supply model with feedback
With feedback applied, the output becomes:
Feedback reduces output disturbances caused by line and load changes by a factor of 1 + GFB × GC(s). Here GFB is the feedback gain, while GC(s) includes the power-stage filter, error amplifier, and any other control-loop gain. Their product is the loop gain. Injecting a signal into the feedback path produces gain and phase Bode plots. The key values are the unity-gain crossover frequency fC and the phase shift at that frequency; phase margin is the difference between that shift and 180°. Transient behavior deteriorates as phase margin approaches 0°. Above the crossover frequency, loop gain falls below unity and feedback provides little additional attenuation of line- or load-transient components.
Relating Frequency Response to Time Response
If one dominant pole controls the loop near the unity-gain frequency and all other poles and zeros are sufficiently remote, the loop gain can be approximated by:
The single-pole response in Figure 3 rolls off at -20 dB per decade and has 90° of phase margin.
Figure 3 Bode plot of a single-pole loop gain
The model shows that loop gain decreases with frequency, so attenuation of the higher-frequency components in a step also decreases. Multiplying the following closed-loop gain factor
by the frequency-domain step 1/s and applying the inverse Laplace transform gives the time-domain response. A load step ΔILOAD produces an exponential recovery. The initial droop is ΔV = ILOAD(s) × ZOUT(s), followed by VFINAL = ΔV × (1 - e^(-t/τ)), where τ = 1/(2πfC). After one time constant, the output has recovered 63% of the initial deviation ΔV.
For an input-voltage step, the output deviation is the product of VIN(s) and GVIN(s). The recovery follows the same law: after τ = 1/(2πfC), 63% of the initial offset has been corrected.
A single dominant pole gives approximately 90° of phase margin and a well-behaved response near crossover. Real loops contain additional poles. When they approach the crossover region, phase margin falls and the step response develops overshoot. Further reduction in phase margin increases ringing; near 0°, oscillation can become sustained. In closed-loop terms, the real component of loop gain becomes negative below 90° of phase margin. As that negative component grows, the closed-loop denominator decreases near crossover and amplifies those frequency components.
A two-pole open-loop model illustrates the effect. Assume 60 dB of dc loop gain and two real poles that influence the crossover region. The open-loop gain is:
The corresponding closed-loop gain is:
The unity-gain crossover lies between ω1 and ω2. Moving the two poles while holding crossover frequency constant changes phase margin. Applying MATLAB step() to 1/(1 + GFB × GC(s)) produces the response family in Figure 4.
Figure 4 Closed-loop responses for different phase margins calculated with MATLAB step()
Figure 4 shows progressively greater overshoot and ringing as phase margin decreases. The system becomes self-oscillatory as the margin approaches 0°. Response initially becomes faster below 90°; in this model, the fastest response without overshoot occurs at approximately 72° of phase margin.
Requirements for a Valid Step Excitation
A useful line or load step must change much faster than the control-loop bandwidth so that it approximates an ideal step. PCB traces and the parasitic inductance, resistance, and capacitance of the components all limit slew rate. Test-board layout and component selection are therefore part of the measurement system.
The required rise time depends on loop bandwidth. A controller switching at 1 MHz normally has loop bandwidth below fSW/2, or 500 kHz. The applied step should contain useful spectral energy to at least fSW/2. Because the maximum slew rate of A × sin(ωt) is A × ω, the corresponding minimum rise time is approximately 1/(πfSW).
Once the target edge time and step amplitude are known, the parasitic limit can be estimated. Suppose a 10 A load step must settle in 200 ns and the path between the load and output capacitor contains 100 nH. Even before switch delay is included, the fastest possible rise time is about 555 ns. If the same 10 A transition is allowed 10 µs, the inductive contribution is about 5% of the total rise time.
Generating an Input Voltage Step
The circuit in Figure 5 switches between two dc supplies with low-RDS(ON) N-channel MOSFETs. During interval A, Q1 connects the device under test to 5 V and Q2 disconnects 3 V. During interval B, Q1 opens and Q2 connects the input to 3 V. Connecting the source of Q2 to 3 V and the drain of Q1 to 5 V prevents unintended body-diode conduction. The gate drive must provide sufficient VGS to turn each device fully on. In systems at 5 V or below, a function generator or MOSFET driver is often adequate. The MAX4428, for example, provides up to 18 V of gate drive, can source or sink 1.5 A, and offers complementary outputs for driving the two FETs out of phase.
If CIN does not need to be mounted directly at the input of the device under test, CIN can be removed from that location and CBP in Figure 5 can serve as the input capacitor. This arrangement makes it easier to provide the capacitance and current needed for a fast input step.
How Parasitics Distort the Step
Parasitic inductance, resistance, and capacitance set both the edge speed and waveform quality. Figure 5 identifies the main parasitic elements in the input-step path. PCB, MOSFET, and capacitor series resistance must be minimized to support high charge and discharge current. A large capacitance driven through a low-resistance path can form an underdamped network, producing LC ringing at the common MOSFET node and the power-supply input. Inductance cannot be eliminated, but it can be reduced until the resonant frequency is well above the bandwidth of interest.
Figure 5 Input-transient generator including parasitic elements
Input Bypass Network Constraints
If CIN must remain directly at the power-supply input for noise or layout reasons, the step generator must charge and discharge it. Producing a change ΔV in time Δt requires a capacitor current of:
CBP should then be much larger than CIN and should use low-RESR ceramic capacitors so that ESR drop remains small at the required current. LESL can still limit the edge when CIN is large. For CIN = 100 µF, ΔV = 1 V, and Δt = 1 µs, the required current is 100 A. With 100 nH between CBP and CIN, raising CIN by 1 V takes about 2 µs. Excess inductance also causes overshoot and ringing. Paralleling several small ceramic capacitors reduces both total RESR and LESL. The path from the bypass capacitors to the MOSFET drains should be short and wide. A 2 mm-wide, 1 oz copper trace has typical parasitic values of about 25 mΩ/cm and 4.75 nH/cm.
MOSFET Selection and Gate Drive Layout
Important MOSFET parameters include RDS(ON), package size, and gate capacitance. RDS(ON), PCB resistance, and bypass-capacitor ESR all limit current into CIN and influence switching overshoot and ringing. Select a low-RDS(ON) device and also minimize the effective drain-source inductance contributed by the package, bond wires, and leads.
Low-RDS(ON) MOSFETs often have higher CGS. Drivers such as the MAX4428 can handle several nanofarads or more, but the driver-to-gate path must still be short and wide to minimize RG and LG and supply the required peak current. Connect the MOSFETs to the bypass capacitor through a low-inductance, low-resistance path. When practical, connect them directly to the power-supply input so that the bypass capacitor also serves as the input capacitor.
Generating a Load Step
A load step can be generated with an N-channel MOSFET operating in its linear-resistance region. Connect the drain to the supply output and the source to ground; VGS then controls the effective load resistance and current. Use a low-inductance current-sense resistor so the measurement loop does not slow the edge or excite ringing between CDS and LPARA. The sense resistor is also part of the applied load. Mount the MOSFET directly at COUT; a small package or parallel devices can further reduce LPARA.
Keep the connection from the pulse generator or gate driver to the MOSFET short and wide to reduce RG and LG. Figure 6 shows the resulting load-transient circuit with its major parasitic elements.
Figure 6 Load-transient test circuit including parasitic elements
MAX1960 Measurement Example
Effect of Phase Margin on Load Response
Figures 7 through 9 show 0 A to 10 A load-step measurements from a MAX1960 voltage-mode buck converter and evaluation board. A high-frequency pole at COMP reduces gain above crossover; placing that pole too low reduces phase margin. Figure 7 has a 42 kHz crossover and 2° of phase margin, and the supply oscillates continuously after the step. Raising the pole frequency increases phase margin. At 11°, sustained oscillation is suppressed, as shown in Figure 8. With 90° of phase margin, the output approaches the single-pole exponential response in Figure 9.
Figure 7 Loop response at 42 kHz crossover and 2° phase margin
Figure 8 Load-step response at 11° phase margin
Figure 9 Single-pole exponential response at 90° phase margin
The load step was generated with an IRLR024N N-channel MOSFET having RDS(ON) = 65 mΩ. The device was placed directly over an output capacitor, with a 37.5 mΩ low-inductance sense resistor between drain and ground. An HP8112 pulse generator switched the gate from 0 V to 4 V and produced a 0 A to 10 A step in 200 ns with almost no added overshoot or ringing.
Figure 10 Input-step response using the same circuit conditions as Figure 9
Figure 10 shows the line-transient response as the input switches between 3.3 V and 5 V. Two IRF3704 N-channel MOSFETs with RDS(ON) = 9 mΩ are connected as in Figure 5 and mounted between the MAX1960 input and two parallel 470 µF Sanyo POSCAP 6TPB470M capacitors. The measured response has an approximately 400 ns rise and a 250 mV amplitude.